1. Field of the Invention
The present invention relates to the field of flat panel display screens. More specifically, the present invention relates to the field of flat panel field emission display (FED) devices.
2. Related Art
An FED device (also called "thin CRT" device) is a thin profile, flat display device which renders an image on a flat viewing surface in response to electrons striking a phosphor layer. Within the FED device, electrons are typically emitted by field emission. An FED device typically contains a faceplate (also called frontplate or "anode") structure and a backplate (also called baseplate or "cathode") structure connected together through a peripheral or outer wall. The phosphor layer is associated with the faceplate while the electrons are emitted from the backplate. The resulting enclosure is held at a high vacuum. To prevent external forces from the ambient pressure of air from collapsing the thin profile display, one or more spacer structures are located between the faceplate and backplate inside the outer wall.
FIG. 1 illustrates a cross sectional diagram of a prior art FED device 5. The FED device 5 includes a faceplate structure 20, a backplate structure 46, a spacer structure 30 and a high voltage supply 56 coupled to the faceplate structure 20 and the backplate structure 46. Although only one spacer 30 is shown, it is appreciated that the FED device 5 may include similar additional spacers (not shown).
Faceplate structure 20 includes an insulating faceplate layer 10 (typically glass material) and a light emitting structure 12 (typically phosphor) formed on an interior surface of the faceplate 20. Light emitting structure 12 typically includes light emissive materials activated by electron bombardment, such as phosphors which define the active region of the FED display 5. Light emitting structure 12 also includes an anode contact (not shown) which is connected to the positive (e.g., high voltage) side of voltage supply 56.
Backplate structure 46 of FIG. 1 includes an insulating backplate 42 and an electron emitting structure 44 located on an interior surface of backplate 46. Electron emitting structure 44 includes a plurality of selectively energized electron-emitting elements 50a-50d which are selectively excited to release electrons which accelerate toward the faceplate structure 20. Electron emitting structure 44 is connected, via a cathode contact, to the low voltage side of the voltage supply 56. Because light emitting structure 12 is held at a relatively high positive voltage (e.g., 0.4-10 kV) with respect to electron emitting structure 44, the electrons released by the electron-emitting elements 50a-50d are accelerated toward corresponding light emissive elements on the light emitting structure 12, thereby causing the light emissive elements (e.g., pixels) to emit light which is perceived by a viewer at the exterior surface of the faceplate 20 (e.g., the flat viewing surface).
Spacer 30 is connected, by a base 30a and a top 30b, between the substantially planar lower surface of light emitting structure 12 and the substantially planar upper surface of electron emitting structure 44. Spacer 30 has a height of H as shown. If spacer 30 is made of a uniform material having a constant resistivity, the voltage distribution along spacer 30 would be approximately equal to the voltage distribution in free space between electron emitting structure 44 and light emitting structure 12. However, in reality, a temperature gradient develops along spacer 30 between its base 30a and its top 30b thereby altering the resistance of the spacer 30. Specifically, energy absorbed by the light emitting structure 12 from the impinging electrons or from the environment acts to warm the top 30b of spacer 30 more than its base 30a. There can be as many as a few degrees Celsius temperature difference between the top 30b and bottom 30a of spacer 30 during normal FED operation.
The material used for spacer 30 generally has a non-zero thermal coefficient of resistivity (TCR). Therefore, the resistivity of spacer 30 varies depending on its temperature. For example, spacer 30 can become less resistive, and thus more conductive, the warmer it is. This example corresponds to a spacer with a negative TCR; spacers with a positive TCR will have a resistance that increases with temperature. As a result, in this example, during display operation, the top 30b of spacer 30 becomes slightly more conductive than its bottom 30a and a resistance gradient (see FIG. 2A) builds up along the height of the spacer 30. Therefore, a larger positive voltage builds up along spacer 30 than would be there under ideal conditions. This larger positive voltage along spacer 30 tends to pull electrons off course that pass nearby and deflects them toward the spacer 30 as shown by an exemplary and exaggerated electron path 34. Because each electron emitting structure 50a is paired with a particular phosphor spot within light emission layer 12, pulling the electron off its intended (straight) path causes a degradation of image quality as the electron misses its designated target. The net effect of the deflection on many electrons is to move the center of brightness of the pixels near the spacer. This appears to the user as dark or light pixel rows at the spacer location.
FIG. 2A, FIG. 2B and FIG. 2C illustrate the temperature and resistance gradients built up along the spacer 30 and their effects on the spacer's voltage. FIG. 2A illustrates a graph 60 having a line 62 which illustrates the resistance gradient along the height of spacer 30 from base 30a (the cathode) to the top 30b (at height H, at the faceplate 20). As shown by the resistance gradient 62, the spacer 30 becomes less resistive closer to its top 30b. Graph 60 also shows the temperature gradient 64 along the height of the spacer 30 from its base 30a (e.g., position 0) to its top 30b (e.g., at height H) near the faceplate 20.
FIG. 2B illustrates a graph 70 of the voltage levels along the height of spacer 30 from position 0 (at base 30a) to position H (at top 30b). Line 74 represents the ideal voltage along the height of spacer 30 assuming a uniform spacer with no temperature gradient. Line 72 is an exaggerated depiction and represents the actual voltage level along the spacer 30 taking into consideration its temperature gradient 64 (FIG. 2A). As shown, the mid point 76 on line 72 has the largest voltage deviation from the ideal voltage line 74. Mid point 76 represents a point along the height of spacer 30 at a height of H/2.
FIG. 2C is a graph 80 illustrating a representation 82 of the voltage error between the actual voltage line 72 and the ideal voltage line 74 (FIG. 2B) along the height of the spacer 30. Graph 80 is very nearly parabolic in shape. The maximum error point 88 is located at the mid point (H/2) because the top 30b and the base 30a of spacer 30 are held at known voltage levels as a result of the voltage supply 56 contacting the spacer 30 at these points. Therefore, the temperature gradient along spacer 30 operates to produce the most positive voltage error at the mid point (H/2) of spacer 30.
Accordingly, it would be desirable to reduce the positive voltage errors (FIG. 2C) that are seen along the height of the spacer 30 so that unwanted electron deflections toward the spacer 30 can be minimized and/or eliminated. By so doing, overall image quality of the FED device can be increased. It would be desirable to provide an FED device that partially compensated for the positive voltage errors along the height of the spacer 30 that are attributed to the temperature gradient of the spacer 30 and to other causes described below. The present invention provides such an advantage. These and other advantages of the present invention not specifically mentioned above will become clear within discussions of the present invention presented herein.